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The sensitivity list for a clocked process should only contain the clock and the reset signals. If you add the wrn and wrk signals to the list, you will create a design that will behave differently in a simulator and on a real FPGA. Quartus will ignore your sensitivity list and just synthesize as if it was (r, clk) so if you want to simulate it correctly in Modelsim you should write it as is in your code.
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If it is a synchronous process, and you add all the signals in the file, it will still behave like a synchronous process, and will still synthesise to a synchronous process, and the synthed design and the simulation will match.
All adding all the extra signals does is cause the simulator to trigger the process when any of the signals changes. But because stuff doesnt actually happen unless there is a rising edge of the clock, nothing actually changes inside the process.
So all you do is add extra work for the simulator to do to action the process when nothing actually happens inside the process.
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