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Altera_Forum
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11 years ago

Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If the examples you are looking at look anything like your code above, I highly suggest you ditch those as very poor examples. There is hardly ever a situation where a variable is required in synthesisable logic. Variables can have issues of you use them wrong that you don't get with signals. Variables are best avoided.

I can't comment on the code about whether you need mixing our anything. I have no idea on the specs of the design. But you should try and register all outputs.