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Altera_Forum
Honored Contributor
Honored ContributorNeed advice about coding style
Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_ForumHonored Contributor
Honored Contributorokay . the second is very bad . You should await that signals comes like clocks - nonsense.
what for the first style, your should capture Enable signal before clock transtion or signal should be stable for clock-period. or must i put multiplexor on data-in? Why I bother vaiables? I follow examples that books and web provide. <- it is common convention :) It seems that i 've alraedy asked similar question. I don't remember where...
