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Altera_Forum's avatar
Altera_Forum
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11 years ago

Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Neither. Why bother using variables at all. You could just sign directly to k or n? Also the codes are not functionally equivalent so you cannot compare them.

Also, assigning signals outside the clocked part or the code is not a recommended style.