Need a help on signalTap clock setting

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The acquisition clock is synchronizid to the 100 MHz clock, so one samples high and two low is just what you should expect. In addition, the sampled data will be wrong in part due to timing violations.

There are only a few cases, where SignalTap acquisition with a clock rate higher than the system clock can be meaningful, e.g. when displaying asynchronous external signals. At worst case, it prevents timing closure of the design and can even cause timing problems in design parts, that are O.K. without SignalTap.

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Understood. Thanks a lot!