Names not found by TimeQuest

Hi Alex, thanks for your response.

The sdc files are freshly generated by QSYS. But meanwhile I found out, that the problem seems to come with the synthesis process. I followed the ways of two signals through the modules. The timing netlist is based on the synthesis result, and the synthesis may remove or replace some signal names for different reasons.

One interface signal from the HPS is simply not used. It's routed by QSYS to the top level and there it is open. I think, that the synthesis process removes the signal completely and so it's not to be found by TimeQuest. But QSYS still generates a constraint with this signal name...

The other HPS interface signal is connected to an I/O pin in the top level module and there it gets the name which I assigned to the I/O pin. When I replace the original name in the QSYS generated constraint by my I/O pin name, it works! I think, that the synthesis replaces the original signal name with my I/O name. With the TimeQuest Name Finder I can find my I/O name, but not the original name from QSYS.

Of course, now I could replace all the concerning signal names in the constraint files by their replacements. But that's a bad solution. Always when the system is newly generated by QSYS I have to patch the files by my own. Or I store my own sdc files in another place and change the project settings for the sdc file path. But then, always when the HSP system configuration was changed, I carefully have to check, if there something has changed in the constraints.

Has someone an idea for a better solution?

Best regards,

Dietmar