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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Yes but I think you have to use the internal memories. You cannot crete a generic size memory.

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You're using an FPGA, so there is no support for a generic size memory. Your inferred memory has to match what exists inside the FPGA.

Cheers,

Dave