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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The only way to have the component ROM compiled correctly is to use: 


	subtype word_t is std_logic_vector(7 downto 0);
	type memory_t is array(127 downto 0) of word_t;

or 


	subtype word_t is std_logic_vector(7 downto 0);
	type memory_t is array(255 downto 0) of word_t;

In all other cases it is not able to create a memory (Memory bits = 0 and M4Ks = 0) and gives the warning "No clocks defined in design".

Is this normal ?