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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you so much for your help. I tried to compile one component at a time and the problem is the "g_ram" component. It uses 0 logic elements and I received this warning "Warning (10631): VHDL Process Statement warning at g_ram.vhd(18): inferring latch(es) for signal or variable "ram", which holds its previous value in one or more paths through the process".