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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok, I opened the design and synthesized it and it uses no logic cells.

If there are no logic cells, then no clock is required :)

Sorry, I don't have time to look at your code in detail. All I can recommend is that you synthesize each component in your hierarchy and make sure each needs logic.

One common mistake to look for is that your reset logic is inverted. However, that type of mistake would be picked up in simulation too.

Good luck!

Cheers,

Dave