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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I already did the testbench and it works properly, but then I slightly modified one component that was not synthesizable (a ram that loads its content from a text file).

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So what happens when you test the modified code with the testbench?

Don't post code inline. No one really wants to read it. If you want someone to look at the problem, post a zip file with the project and a synthesis Tcl script, or post a .qar file.

Cheers,

Dave