My clock port cannot be matched as a port

Hmm, that is weird then. I would ask if you've actually used it as a clock, but your RTL view implies you are.

Could you post the body of your code please.

Before synthesis, its always a good idea to check the functionality of your logic using Modelsim and a testbench. If you've got a logical error that causes Quartus to determine that CLOCK_50 is not used for anything, then perhaps it is eliminating the clocked logic, and hence you no longer have a clock in your design.

And looking at your warnings file:

Warning (15610): No output dependent on input pin "CLOCK_50"

You see your problem :)

Cheers,

Dave