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Honored Contributor
Honored ContributorMutiplexer giving high impedance while connected serially to a D-Flip Flop
Hi guys, I am very much new to verilog and I have been trying to replicate an LUT-FF pair with a multiplexer to select the output from either directly from the LUT or from the D-FF. When I trie...
Altera_ForumHonored Contributor
Honored ContributorHi!
The "always@(posedge clk or negedge reset)" statement should be "always@(posedge clk or posedge reset)" as you trigger on a rising reset input. And you should use a complete sensitivity list (all signals at the right side of "=") at: "always@(sel)". Or the simple way: "always @*" Use "=" instead of "<=" in combinatorial blocks ("always @*"). With these changes your output should be 1'b0 or 1'b1 instead of x.
