Forum Discussion
Contributormultiple drivers due to conflicting nodes
Thanks for your design.qar files.
This seems to be a bug in the standard where the error does not report the correct place.
If you use pro edition, you will see the error more accurate.
The Error mention is because you have multiple driver toward dataIN. In your SystemVerilogTest1.sv, go to line 142, comment out //assign dataBus = ( chipSelectRAM ) ? dataOut : 16'bZZZZZZZZZZZZZZZZ; // Do I need to include iSDRAMWriteRequest here??
You will see that the synthesis passed.
How do you check if this datain have multiple driver, you can run elaboration. Go to rtl viewer, look for the signal datain and you will see there are two driver driving it. Attached screenshot.
Super ContributorThanks for your design.qar files.
This seems to be a bug in the standard where the error does not report the correct place.
If you use pro edition, you will see the error more accurate.
The Error mention is because you have multiple driver toward dataIN. In your SystemVerilogTest1.sv, go to line 142, comment out //assign dataBus = ( chipSelectRAM ) ? dataOut : 16'bZZZZZZZZZZZZZZZZ; // Do I need to include iSDRAMWriteRequest here??
You will see that the synthesis passed.
How do you check if this datain have multiple driver, you can run elaboration. Go to rtl viewer, look for the signal datain and you will see there are two driver driving it. Attached screenshot.
ContributorThanks @KennyTan_Altera . I will mark your response as the accept solution. The more I look at my code, the more ridiculous it is.. but that's what happens when you get confused about what you can and cannot do.
I still don't understand why some of those registers were removed from my design. I can only assume it's Quartus attempting to optimise redundant logic and throwing it away.
Now that I understand what the basic problem is, I can move forward. My VGAController is doing the wrong thing anyway. I've replaced the chipSelectRAM and chipSelectVGA with a 2-bit value of enums so chipSelect is mutually exclusive for my modules. Having 2 separate logic flags I ran the risk of both chipSelectXXX flags being high at the same time.
Thanks again for your help.
