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Altera_Forum's avatar
Altera_Forum
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12 years ago

multiple clock problem

Hey! I am a beginner in VHDL programming and would like to ask a question to more advanced users. I am trying to write a simple shift register in order to control the stepper motor. Everything was ok...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

And what logic do you expect this to map to? The registers on FPGA only have a single clock, so 4 clocks are not allowed. And you can only use either rising or falling edge, not both.

WHat I think you want to do is generate clock enables and clock the design on the system clock.