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Altera_Forum
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8 years ago

Multiple builds of the same design has different timing closure results

Hi, I ve been working on a project, which had some difficulty in timing closure. Among the other tool options, i learned to use SEED_VALUE, to start the synthesis and route options with a seed...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Are they 100% the same? If there is so much as a different name on a wire, you will get different results. I tried to explain why in the following:

http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps

Also, there can be IP that changes, specifically an ID IP in QSYS. (I can't remember the name off the top of my head). But something like that changes based on the time you compile, so all results are always different.

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Thanks Rysc, for your quick reply. Yes we are using licensed IP cores from altera for our project namely, Triple Speed Ethernet Megafunction, and NIOS-II cores. Is there anything that could be done to get consistent builds for the same design in such a case?.

Regards

Jeebu Jacob Thomas