Multi-jtag server configuration

Our modules are purely custom. Pactron is assembling them. Here's a rough overview: http://www.altera.com/end-markets/computer-storage/qpi/quick-path-interconnect.html

These essentially sit in the second socket of a 2 CPU Xeon server, and communicate via the QPI bus protocol (single link). As this link is established very early in the bios during power-on, we have to make custom modifications to the bios to wait for the FPGA to program and establish this link. Future designs will have the bios program the FPGA through the CPU without the need for jtag, but this is what we are currently deploying for development. We have also been shipping these to customers in small volumes, so I am sure they would also be interested in this solution. Redesign of the module is NOT an option.