Forum Discussion
Altera_Forum
Honored Contributor
11 years agoFirst, let me state that I am a systems administrator and lab manager, not a hardware engineer.
Our module has a 10 pin header for the USB Blaster to plug into for programming and probing the FPGA. We currently have 24 systems with modules, and due to the configuration the module needs to be programmed while the system bios is in a loop waiting for discovery. The systems currently are not self-programming, thus the need for Quartus on a 'Host' system. We have a team of engineers doing various debug and optimizations of our base RTL, thus the reason for Signal Tap and reprogramming (which takes ~30-40 seconds vs 3-5 minutes converting to POF and programming that way). When the engineers are not programming or debugging, the systems are in a pool for automated regression testing. When they need a system, they can request one from the pool. We are also ramping up to allow other internal (and possibly external) groups access these systems. Due to the space needed (4U rack space per FPGA based system), we need to be as conservative as possible. Hence the 1U 'JTag Server' in my diagram. Having a dedicated system running JTAG for each FPGA based system is not scalable, space or administratively.