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amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago
Solved

Multi-driven nets -> how to report ?

Hi All, How is it possible to report the multi-driven nets in the design? Should these nets appear in the synthesis log? Thank you!
  • Nurina's avatar
    Nurina
    3 years ago

    Hello,


    Multi-driven nets are not allowed in VHDL/Verilog HDL/SystemVerilog at all, you will receive below error during Synthesis and this will effectively stop the compilation, there won't be any reports because of that.


    Error (10028): Can't resolve multiple constant drivers for net


    So, if you don't receive this error then there is no multi-driven nets in your RTL code.


    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey.


Best regards,

Nurina