Forum Discussion
Altera_Forum
Honored Contributor
12 years agoOk: Challenge for you to help improve your VHDL further:
1. Try and re-write this block without your custom adder component 2. Now try it without using the hellish type that is altera's "std_logic_2d" type (hint: create you own type). Even preferably avoid std_logic_vector completly for any numerical values (it just adds to type conversions). The std_logic_2d type was creates by altera to try and be compatible with their graphical design files and AHDL. It is horrible to use, as you have found out as you have to pick it apart bit by bit.