Forum Discussion
Altera_Forum
Honored Contributor
12 years agoNo, the question is why is there no register after the adder at the output? Its usually best practice to have a register as the last bit of logic before a signal leaves a block.
I just feel simple components (like a single adder) help obfuscate the design heirarchy, when a simple + function can be used. I dont understand the relevance of the inputs being odd or even? Altera already provides a parrellel add megafunction: http://www.altera.co.uk/literature/ug/ug_lpm_alt_mfug.pdf