Multi cycle path trough combinatoric logic circuit

Thanks for fast replay.

I will start with easy part.

--- Quote Start ---

I notice the data out from your blcok is not registered - any reason?

--- Quote End ---

Output data will be registered in the next module.

--- Quote Start ---

What you need to do, is set the setup and hold times either "from" the input registers or "to" the output registers (or from and to if you only want specified paths.

set_multicycle_path -from [get_keepers {my_input_regeres} ] -to [get_keepers {my_output_registers}] -setup N

set_multicycle_path -from [get_keepers {my_input_regeres} ] -to [get_keepers {my_output_registers}] -hold N-1

This is when enable is high once every N clocks.

--- Quote End ---

Yea it helped, but with some modifications:

I looked in Altera home page and finally found SDC example where enable signals was used.

http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html#figure1 (http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html#figure1)

Applied same technique to my design and get such result

set_multicycle_path -to [get_fanouts [get_pins -hier *en_in*] -through [get_pins -hier *|*ena*]] -setup 5

set_multicycle_path -to [get_fanouts [get_pins -hier *en_in*] -through [get_pins -hier *|*ena*]] -hold 4

https://www.alteraforum.com/forum/attachment.php?attachmentid=8324

So is it correct? To my mind yes!