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Altera_Forum
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12 years ago

Multi cycle path trough combinatoric logic circuit

Hi, i have an issue to fully understand and constraint multi cycle path for particular vhdl file. I created pipeline tree adder with enable input. This pipeline tree adder is created using recu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

What you need to do, is set the setup and hold times either "from" the input registers or "to" the output registers (or from and to if you only want specified paths.

set_multicycle_path -from [get_keepers {my_input_regeres} ] -to [get_keepers {my_output_registers}] -setup N

set_multicycle_path -from [get_keepers {my_input_regeres} ] -to [get_keepers {my_output_registers}] -hold N-1

This is when enable is high once every N clocks.

I notice the data out from your blcok is not registered - any reason?