Multi-channel FIFO will not generate with Qsys (bug in Quartus Prime 16.1.2?)

****UPDATE 21FEB2017**** I went ahead and submitted a trouble ticket to the Altera helpdesk. This has been forwarded to the developer for both a fix and a temporary work-around.

I found that the Avalon Streaming Multi-Channel FIFO fails to generate for both my project and a brand new blank one. I get the same exact error message. Perhaps a bug in Qsys/Quartus 16.1.2? Or I could just be doing something wrong.

The following error is recieved when generating from Qsys using Quartus Prime 16.1.2:

Error: mc_fifo: wrong#  args: should be "generate output_name" while executing "generate synth altera_avalon_multi_channel_shared_fifo"
Where "mc_fifo" is the qsys module name Avalon Multi-Channel Shared FIFO

Doing some searching, this problem of wrong# args seems to come up when there is a space in a name. My directory though is C:\Users\Joseph\Documents\local_repos\he_mt6d.

I've attached a copy of the error (both my project and the blank project), a snapshot of the bare-bones Qsys instantiation, and the verilog code and tcl from C:\intelFPGA\16.1\ip\altera\sopc_builder_ip\altera_avalon_multi_channel_shared_fifo.

Does anyone have any success with this module or know how to diagnose wrong# args: should be "generate output_name" problem from a system component from the IP catalog?