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Hi,
I found that
1) mSGDMA core gets easier to operate correctly when I turn off "burst enable."
2) However, sometimes the mSGDMA with burst disabled can fail to transfer data.
With signal-tap II, I found that this failure is caused by incorrect latch to length_counter and/or
address_counter in Write_master. For example, when descriptor port of Dispatcher receives
0x0001_4000 as a length, 0x0000_4000 is written into the length_counter in Write_master
of a ST-MM mSGDMA. Since MM-ST mSGDMA sends 0x0001_4000 elements of data to the
ST-MM mSGDMA, the former mSGDMA is kept busy. And then the next DMA transfer fails.
"src_write_master_data" (a command from Dispatcher to Write_mater) has a length of
0x0000_4000, instead of 0x0001_4000. So Dispatcher wrongly works. I doubt
the_write_signal_breakout module in the_descriptor_buffers module.
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I solved the problem by implementing my own fifo_with_byteeable that does not use alt_syncram with byteenable.
So I conclude that incorrect write with byteenable of the altsyncram on Sratx V 5SGXEA7 causes the problem.
If you want to read my fifo_with_byteenables, please let me know.
Mickycat
Honored Contributor
