mSGDMA: Incorrect operation but the behavior changes when SignalTapII is inserted.

Hi,

I found that

1) mSGDMA core gets easier to operate correctly when I turn off "burst enable."

2) However, sometimes the mSGDMA with burst disabled can fail to transfer data.

With signal-tap II, I found that this failure is caused by incorrect latch to length_counter and/or

address_counter in Write_master. For example, when descriptor port of Dispatcher receives

0x0001_4000 as a length, 0x0000_4000 is written into the length_counter in Write_master

of a ST-MM mSGDMA. Since MM-ST mSGDMA sends 0x0001_4000 elements of data to the

ST-MM mSGDMA, the former mSGDMA is kept busy. And then the next DMA transfer fails.

"src_write_master_data" (a command from Dispatcher to Write_mater) has a length of

0x0000_4000, instead of 0x0001_4000. So Dispatcher wrongly works. I doubt

the_write_signal_breakout module in the_descriptor_buffers module.

The both MM-ST and ST-MM mSGDMAs are operating at 200MHz of afi_clk of DDR3 Uniphy

memory controller. The DDR3 memories operate correctly, because I can transfer data between

a host PC and the FPGA via PCI-Express. So I doubt something like timing-violation, while

TimeQuest saids no negative slack found for all clocks and conditions.

(I rechecked all the timing constraints are given sufficiently.)

Are there anyone who experienced similar phenomena?

Your any information is very helpful.

--

Mickycat