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Sometimes, I'm just completely clueless on how to even approach a problem in VHDL and the building block style of schematic seems like an easier way to go about it.
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I'll typically draw a block diagram with counters and data path logic, then draw the waveforms that logic needs to work, and then start writing an HDL design along with its testbench. I then "fill in the details" by adding new test sequences, and adding FSM states and datapath controls until the logic is correct. For example, read through this document ...
http://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf Cheers,
Dave
Honored Contributor
