Forum Discussion
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- Signal tap does not want you to derive a signal with combinatorial logic and call that a clock. That would messes up the timing. --- Quote End --- Thanks, Randall for this pointer. I found out I could use CLOCK_50 ~ 50MHz for the acquisition clock... I owe my ST knowledge to you! --- Gsynth, in your code --- I broke the chain and unclocked it to see the propagation delay through the chain. you are right, apart from the first LCELL which has a considerable propagation delay (don't know why), the remaining transitions happen really fast.... I tried it on chip with Signal Tap [I know how it works now, yaay] and the transitions seem to happen almost simultaneously. I wonder where my delay is going to come from, at this rate. :(