more questions about signal tap

Just a heads up - the ring is going to need to be pretty big to get down to 100MHz for Signal Tap sampling. Cyclone II reports this 25 cell path at 91MHz. This is a worst case guarantee, actual silicon speed will be faster.

---

module test (clk,out);

input clk;

output out;

reg out;

wire [24:0] stall /* synthesis keep */;

assign stall[24:0] = {stall[23:0],out};

always @(posedge clk) begin

out <= stall[24];

end

endmodule