Moore Finite State Machine questions (VHDL and C)

Hello Tricky , thanks for your reply. I am aware that I am describing hardware, but I am still a big novice. Im using that waveformgenerator because we used it on my university first time when I came in touch with vhdl/verilog to test easy circuits.

Currently I have a block diagram in my eye's mind how to implement it (reffering to literature). I just like to describe this behaviour I ve mentioned in my first post.

Here s a small cutaway for the nextstate logic.

---------------------------------------------

state : process(clk,rst)

begin

if(rst='1') then

current_fsm_state<=RESETSTATE;

--current_internal_cnt<="00";

elsif(rising_edge(clk)) then

current_fsm_state<=next_fsm_state;

--current_internal_cnt<=next_internal_cnt; -- -- i have also tried it with that signal assignment to check against it

end if;

end process;

p_output: process(current_fsm_state)

begin

case current_fsm_state is

when RESETSTATE =>

error_output<='0';

when State_A =>

--

-- dont wanna spam the complete code

end case;

end process;

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Do u have some ideas how to implement or avoid this scenario?