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Altera_Forum's avatar
Altera_Forum
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16 years ago

Modelsin Simulation error - alt_inbuf is not bound

Dear Gurus,

I have been writing several small VHDL files and test benching them individually with success. I have created the design in quartus and tried File -> Create/Update -> Create HDL Design File for Current File to export the design. When I try to simulate the test bench for the overall design I get many errors like

component instance b2v_inst5 alt_inbuf is not bound.

I am seeking documentation for simulating the top level but if anyone can shed any light on this issue, I would be grateful.

Best regards,

H

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It may be the case, that some libraries have not been compiled in your Modelsim ínstallation, in this case altera_primitives_components, that contains alt_inbuf. It may be a special problem with VHDL files originated from schematic entry, because these primitives aren't used in generic VHDL code, I think.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Dear FvM,

    You hit the nail on the head. I hadn’t referenced the altera library so adding USE altera.all to my test bench the design now simulates.

    Thanks once more for your patients and help.

    Best regards,

    H