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Altera_Forum
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16 years ago

Modelsin Simulation error - alt_inbuf is not bound

Dear Gurus, I have been writing several small VHDL files and test benching them individually with success. I have created the design in quartus and tried File -> Create/Update -> Create HDL De...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Dear FvM,

You hit the nail on the head. I hadn’t referenced the altera library so adding USE altera.all to my test bench the design now simulates.

Thanks once more for your patients and help.

Best regards,

H