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Altera_Forum
Honored Contributor
Honored ContributorModelsim won't compiles VHDL -> Unexpected signal: 11
Hi Altera, some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code. library ieee;
use ieee.std_logic_1164.all;
entity x is
generic (signal_count ...
Altera_ForumHonored Contributor
Honored ContributorAgain - this is a defect. You need to raise the issue with altera.
