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Altera_Forum
Honored Contributor
Honored ContributorModelsim won't compiles VHDL -> Unexpected signal: 11
Hi Altera, some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code. library ieee;
use ieee.std_logic_1164.all;
entity x is
generic (signal_count ...
Altera_ForumHonored Contributor
Honored ContributorInteresting that Questa doesn't have this problem.
So far i tried to compile it within a ModelSim project, outside a project file environment and into a clean newly created work library. It doesn't changes the result and always comes up with the signal 11. Only if i change the source from the double array range code to a single array access with individual bit access it compiles.
