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Altera_Forum
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10 years ago

Modelsim won't compiles VHDL -> Unexpected signal: 11

Hi Altera, some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code. library ieee; use ieee.std_logic_1164.all; entity x is generic (signal_count ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you for the clarification. I wasn't sure if modelsim altera edition is managed by altera or by mentor.

I haven't got the 10.4c for now, but testing with 10.4b shows the same behavior.

Let's see what mentor says to this.