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Altera_Forum
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10 years ago

Modelsim won't compiles VHDL -> Unexpected signal: 11

Hi Altera, some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code. library ieee; use ieee.std_logic_1164.all; entity x is generic (signal_count ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Looks like a Modelsim bug. Fatals like that without a decent explanation usually are.

Have you tried 10.4c? (the latest version)

If it still fails with latest you need to raise a ticket with mentor (not altera)