Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorModelsim won't compiles VHDL -> Unexpected signal: 11
Hi Altera, some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code. library ieee;
use ieee.std_logic_1164.all;
entity x is
generic (signal_count ...
Altera_ForumHonored Contributor
Honored ContributorLooks like a Modelsim bug. Fatals like that without a decent explanation usually are.
Have you tried 10.4c? (the latest version) If it still fails with latest you need to raise a ticket with mentor (not altera)
