Modelsim vs. Quartus II Simulator

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One of the biggest differences between the Q2 simulator and Any of the simulation tools using testbench files is that you can design your testbench file to react to outputs from the Unit Under Test.

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So Bob, what is the difference between the wvf file and a generic Verilog test bench?

I opened one of the wvf files and it is a simple text file. I also noticed that Q2 simulator asks for "test" file, and by definition one must provide a wvf file as an input to the simulation.

That is where I get confused?

Thx