Forum Discussion
Altera_Forum
Honored Contributor
18 years agoOne of the biggest differences between the Q2 simulator and Any of the simulation tools using testbench files is that you can design your testbench file to react to outputs from the Unit Under Test. In other words the testbench can simulate the devices the FPGA is connected to. Years ago I had to design my Q2 sims by running them for an amount of time, seeing the output change and note the point it does, modify the sim input to react to the change then run till the next change. Now I just write the responses into the testbench and only change it when the testbench is wrong.