Forum Discussion
Altera_Forum
Honored Contributor
15 years ago1) I think it's propagation delay. And you can move on wirth your design.
2) You should never design without a reset value and never simulate without applying a reset for a sufficnet long period of time. 3) The initial value, to the best of my knowledge, is not sythesized and only creates discrepancies between RTL and gate level simulations. 4) Never assume that somthing has a given value 'at startup'. It's your reset that fix the design to a known state