Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI tried removing that and tried delaying the clock and reset as FvM suggested. The best I could do was reduce the undefined 'count' value to the first 5ns. Basically, what I am seeing is that for any register in the test bench module, the values are defined starting at t=0. For any instantiated entity, its output does not become valid until a few nanoseconds later. I am not sure if 5ns is due to propagation delay in this case, since that sounds like too long. If that is normal, then I will probably just move on since the simulation looks correct past the first few nanoseconds.
nplttr: I thought the initial block is synthisized. I usually have a auto reset scheme based on a count that makes sure everything is what it is supposed to be at startup. Is that a sound way of doing it or do you recomment a better way - in that absense of an external reset that is.