Forum Discussion
Altera_Forum
Honored Contributor
15 years agoProbably you see undetermined results due to propagation delay of the signal in your logic (you need some time before the reset propagates to the output).
However the way you define your testbench is awkward. Better use a process for the clock: always begin clk=1'b0;# 10; clk=1'b1;# 10; end This will be repeated forever then the initial block, that is processed only once at the beginning of the simulation: initial begin reset=1'b1;# 105; reset=1'b0;# 1000; $stop; end Try this (if I didn't make too many mistakes in the code)