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Altera_Forum's avatar
Altera_Forum
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15 years ago

ModelSim Timing Simulation Error : DFFEAS HOLD Violation

Hi everyone,

I got a warning message when I tried to perform Gate Level Simulation in my design.

It said like this :

*/DFFEAS HOLD high VIOLATION ON DATAIN WITH RESPECT TO CLK;

Expected := 0.157 ns; Observed := 0.074 ns; At 42067.518 ns

I got so many warning message like above.

when I right clicked in the message and select "View Verbose Message", a dialog box opened and said "VHDL Vital timing check violation."

Is there anyone here has a clue about what happened above? Solution?

It makes my design stop work in my simulation.

Please help me...

Thanks... :)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hi, there,...

    what kind of information do you need?

    how about simulation screenshot?

    I create red circle in the picture as indicator warning location.

    here I attach it.

    thanks...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    hi, there,...

    what kind of information do you need?

    how about simulation screenshot?

    I create red circle in the picture as indicator warning location.

    here I attach it.

    thanks...

    --- Quote End ---

    Hi,

    the message means that you have timing violation in your design. Go into your project and

    have a look to your timing analysis results. I'm quite sure that you will find hold time violation in the results. You have to solve this timing violation in your design first.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    I would like to know if you've solve your problem because I've got the same problem on mine design.