Modelsim Simulation VHO vs VHDL files

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This is likely your problem:

wait for SYS_CLK_period*10;

Doing this means the SubBytes_IN and CORRECT_OUTPUT signals will change just before the clock changes, making it look like it a pipeline stage has dissapeared.

Instead, do this:

for i in 1 to 10 loop
  wait until rising_edge(SYS_CLK);
end loop;

While waiting in a testbench - if the inputs are related to the clock, always wait for the clock - dont wait for a specific time.

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Yes you are right! The wait for period and wait for an event does make a difference here.