Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Modelsim Simulation VHO vs VHDL files

I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

This is likely your problem: 


wait for SYS_CLK_period*10;

Doing this means the SubBytes_IN and CORRECT_OUTPUT signals will change just before the clock changes, making it look like it a pipeline stage has dissapeared.

Instead, do this: 


for i in 1 to 10 loop
  wait until rising_edge(SYS_CLK);
end loop;

While waiting in a testbench - if the inputs are related to the clock, always wait for the clock - dont wait for a specific time.