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Altera_Forum
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9 years ago

Modelsim Simulation VHO vs VHDL files

I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Have you re-assigned the clock anywhere internally other than the port maps, like: 


my_internal_clock_signal <= sys_clk;

Can you post the code for your testbench?

Without the code - we can only guess.