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Altera_Forum
Honored Contributor
Honored ContributorModelsim Simulation VHO vs VHDL files
I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_ForumHonored Contributor
Honored ContributorHave you re-assigned the clock anywhere internally other than the port maps, like:
my_internal_clock_signal <= sys_clk;
