Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorModelsim Simulation VHO vs VHDL files
I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_ForumHonored Contributor
Honored ContributorWhat you have posted is fairly meaningless without the code. But you say they design was asynchronous, but every component uses a clock - is it not synchronous?
