Modelsim Simulation VHO vs VHDL files

The simulation from the compiled VHO files will reflect what is likely to happen on the chip. If it is asynchronous then I suspect you didnt take into account logic path delays in your design.

Asynchronous designs are tricky to work with as they are full of race conditions and timing issues, and can be affected by PVT (process, voltage, temperature). I highly suggest you synchronise your design (what FPGAs are designed for) as it makes a design predictable.

It might be worth posting your code to see if we can see any problems with it.