--- Quote Start ---
If the file from Quartus is a netlist, and you get differences in your simulation, then I suggest that you have a problem in your design.
Is your design fully synchronous? Does it have lots of asynchronous logic? Have you got all of the appropriate signals in sensitivity lists?
--- Quote End ---
Hi, thanks for the reply. The design is asynchronous. and yes I do suspect something wrong with my design. Which one reflects the real outcome from my design? The simulation from VHO file or File Simulation.
I also realized the waveform from VHO Simulation is one cycle delayed compared to the simulation directly from VHDL File :(
Honored Contributor
