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Altera_Forum
Honored Contributor
Honored ContributorModelsim Simulation VHO vs VHDL files
I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_ForumHonored Contributor
Honored ContributorIf the file from Quartus is a netlist, and you get differences in your simulation, then I suggest that you have a problem in your design.
Is your design fully synchronous? Does it have lots of asynchronous logic? Have you got all of the appropriate signals in sensitivity lists?
