ModelSim simulation result is different to run in real FPGA

The ADC's SPI data are first driven by the falling edge of the FS signal, then each falling edges of SCLK which speed is equal to clk_reg. That is, the ADC sends out data on falling edga of clk_reg, and the state machine reads data on rising edge of clk_reg. The system clock (clk_reg) has period of 40 ns (25 MHz). Therefore, there are 20 ns for the ADC new data delay (tPPDO 17 ns max), and > 20 ns For the first bit delay (tDMSB 12 ns max).

The ADC SPI timing diagram:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7748

When read data from PC IO (state_read), We need to check signals only when bs_reg and rd_reg are both low, so we need to watch and let only bs_reg and rd_reg in the sensitivity list. We also tried to disable the state_read, let result of read SPI data output to data bus, and confirmed the state_read does not affect the problem of data shift.

Most of the latches left in the state_machine are consider as required. However we continue to review those code which maybe hide problem.

Thank you for help!